CY7C128A-25LMB 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C128A-25LMB Datasheet PDF : 9 Pages
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CY7C128A
AC Test Loads and Waveforms
5V
OUTPUT
R1 481Ω
5V
OUTPUT
R1 481Ω
30 pF
INCLUDING
JIG AND
SCOPE (a)
R2
255 Ω
5 pF
INCLUDING
JIG AND
SCOPE (b)
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
R2
255 Ω
C128A–4
3.0V
10%
GND
≤ 5 ns
ALL INPUT PULSES
90%
90%
10%
≤ 5 ns
C128A–5
Switching Characteristics Over the Operating Range[2,6]
7C128A–15 7C128A–20 7C128A–25 7C128A–35 7C128A–45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
20
25
35
45
ns
tAA
Address to Data Valid
15
20
25
35
45 ns
tOHA
Data Hold from Address Change 5
5
5
5
5
ns
tACE
CE LOW to Data Valid
15
20
25
35
45 ns
tDOE
OE LOW to Data Valid
10
10
12
15
20 ns
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[7]
CE LOW to Low Z[8]
CE HIGH to High Z[7,8]
3
3
3
3
3
ns
8
8
10
12
15 ns
5
5
5
5
5
ns
8
8
10
15
15 ns
tPU
CE LOW to Power-Up
0
0
0
0
0
ns
tPD
CE HIGH to Power-Down
WRITE CYCLE[9]
15
20
20
20
25 ns
tWC
Write Cycle Time
15
20
20
25
40
ns
tSCE
CE LOW to Write End
12
15
20
25
30
ns
tAW
Address Set-Up to Write End
12
15
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
20
20
ns
tSD
Data Set-Up to Write End
10
10
10
15
15
ns
tHD
tHZWE
Data Hold from Write End
WE LOW to High Z[7]
0
0
0
0
0
ns
7
7
7
10
15 ns
tLZWE
WE HIGH to Low Z
5
5
5
5
5
ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
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