MB91121 데이터 시트보기 (PDF) - Fujitsu

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MB91121

32-bit RISC Microcontroller

Fujitsu 

MB91121

(Continued)

Pin no.

Pin name

47 DACK1/PE5

48 EOP1/PE6

49 DREQ2/PE7

50 DACK2/PI0

51 EOP2/ATG/PI1

53 X1

54 X0

56 RAS0/PB0

57 CSOL/PB1

58 CSOH/PB2

59 DW0/PB3

60 RAS1/PB4

61 CS1L/PB5

62 CS1H/PB6

63 DW1/PB7

65 CS0

Circuit type

Function

[DACK1] DMAC external transfer request acknowledge output

(ch1) . This function is enabled with the DMAC transfer request ac-

knowledge output flag set to “Enabled”.

F

[PE5] General-purpose I/O port. This function is enabled with the

DMAC transfer request acknowledge output flag or DACK0 output

flag set to “Disabled”.

[EOP1] DMAC EOP output (ch1) . This function is enabled with

F

the EOP output flag set to “Enabled”.

[PE6] General-purpose I/O port

[DREQ2] DMA external transfer request input (ch2) . Since this

input is used whenever the DMA external transfer request has

F

been selected as a DMA transfer trigger event, the output by the

other function must remain off unless used intentionally.

[PE7] General-purpose I/O port

[DACK2] DMAC external transfer request acknowledge output

(ch2) . This function is enabled with the DMAC transfer request ac-

knowledge output flag set to “Enabled”.

F

[PI0] General-purpose I/O port. This function is enabled with the

DMAC transfer request acknowledge output flag or DACK0 output

flag set to "Disabled".

[EOP2] DMAC EOP output (ch2) . This function is enabled with

the EOP output flag set to “Enabled”.

[ATG] A/D converter external trigger input. Since this input is used

F

whenever the A/D converter external trigger signal has been se-

lected as an A/D trigger event, the output by the other function

must remain off unless used intentionally.

[PI1] General-purpose I/O port. This function is enabled with the

DMAC transfer termination signal output flag set to “Disabled”.

A

Clock (oscillation) output.

Clock (oscillation) input.

RAS output of DRAM bank 0

CASL output of DRAM bank 0

CASH output of DRAM bank 0

F

WE output of DRAM bank 0 (Low active)

RAS output of DRAM bank 1

[PB0 to PB3] Can serve as a port when not used for signal output.

CASL output of DRAM bank 1

CASH output of DRAM bank 1

F

WE output of DRAM bank 1 (Low active)

[PB5 to PB7] Can serve as a port when not used for signal output.

M

Chip select 0 output (Low active) .

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