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CY7C1338B 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1338B
128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
Cypress Semiconductor
CY7C1338B Datasheet PDF : 18 Pages
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Timing Diagrams
(continued)
Read Cycle Timing
[13, 15]
CY7C1338B
CLK
Single Read
t
CYC
t
CH
Burst Read
Unselected
Pipelined Read
t
ADS
t
ADH
t
CL
ADSP ignored with CE
1
inactive
ADSP
t
ADS
ADSC
ADV
t
ADVS
t
ADH
t
AS
t
ADVH
ADD
RD1
RD2
t
AH
GW
t
WS
t
WH
WE
CE
1
t
CES
t
CEH
ADSC initiated read
Suspend Burst
RD3
t
WS
t
WH
CE
1
masks ADSP
CE
2
t
CES
CE
3
t
CES
OE
Data Out
Unselected with CE
2
t
CEH
t
CEH
t
EOV
t
OEHZ
t
CDV
11aa
t
CLZ
t
DOH
2a
2b
= DON
’
T CARE
2c
2c
2d
= UNDEFINED
3a
t
CHZ
Note:
15. RDx stands for Read Data from Address X.
Document #: 38-05143 Rev. **
Page 11 of 18
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