CY7C1338G-100AXC(2006) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1338G-100AXC
(Rev.:2006)

4-Mbit (128K x 32) Flow-Through Sync SRAM

Cypress Semiconductor 

CY7C1338G

Timing Diagrams

Read Cycle Timing[17]

tCYC

CLK

ADSP

ADSC

t CH t CL

tADS tADH

tADS tADH

tAS tAH

ADDRESS

GW, BWE,BW

[A:D]

CE

ADV

A1

A2

t WES tWEH

tCES tCEH

t

ADVS

tADVH

ADV suspends burst.

Deselect Cycle

OE

Data Out (Q)

tOEV

High-Z

tCLZ

tCDV

tOEHZ

Q(A1)

Single READ

tOELZ

tCDV

tDOH

Q(A2) Q(A2 + 1)

Q(A2 + 2)

BURST

READ

Q(A2 + 3)

Q(A2) Q(A2 + 1)

Burst wraps around

to its initial state

tCHZ

Q(A2 + 2)

DON’T CARE UNDEFINED

Note:

17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05521 Rev. *D

Page 11 of 17

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