CY7C1324F 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

제조사

CY7C1324F

2-Mb (128K x 18) Flow-Through Sync SRAM

Cypress Semiconductor 

Timing Diagrams (continued)

Write Cycle Timing[15, 16]

tCYC

CY7C1324F

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A:B]

GW

CE

ADV

t

CH

t CL

tADS tADH

tADS tADH

tAS tAH

A1

A2

Byte write signals are ignored for first cycle when

ADSP initiates burst.

tCES tCEH

t

WES

t

WEH

ADSC extends burst.

tADS tADH

A3

tWES tWEH

tADVS tADVH

ADV suspends burst.

OE

tDS t DH

Data in (D)

Data Out (Q)

High-Z

D(A1)

tOEHZ

BURST READ

Single WRITE

D(A2)

D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3)

BURST WRITE

DON’T CARE UNDEFINED

Note:

16. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW...

D(A3)

D(A3 + 1) D(A3 + 2)

Extended BURST WRITE

Document #: 38-05431 Rev. **

Page 11 of 15

Share Link: