CY7C1324F 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1324F Datasheet PDF : 15 Pages
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CY7C1324F
Pin Descriptions
Name
A0, A1, A
BWA,BWB
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
ADSC
ZZ
DQs
DQPA, DQPB
VDD
VSS
TQFP
I/O
Description
37,36,32,
Input- Address Inputs used to select one of the 128K address locations. Sampled at
33,34,35, Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
44,45,46,
are sampled active. A[1:0] feed the 2-bit counter.
47,48,49,80,
81,82,
99,100
93,94,
Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
88
Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge
Synchronous of CLK, a global Write is conducted (ALL bytes are written, regardless of the values
on BW[A:B] and BWE).
87
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a Byte Write.
89
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
98
Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH.
97
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
92
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
86
Input- Output Enable, asynchronous input, active LOW. Controls the direction of the
Asynchronou I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
s
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a Read cycle when emerging from a deselected state.
83
Input- Advance Input signal, sampled on the rising edge of CLK. When asserted, it
Synchronous automatically increments the address in a burst cycle.
84
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH
85
Input- Address Strobe from Controller, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
64
Input- ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronou non-time-critical “sleep” condition with data integrity preserved. For normal
s
operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
58,59,62,63,
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register
68,69,72, Synchronous that is triggered by the rising edge of CLK. As outputs, they deliver the data
73,8,9,12,
contained in the memory location specified by the addresses presented during the
13,18,19,22,
previous clock rise of the Read cycle. The direction of the pins is controlled by OE.
23
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
24,74
DQP[A:B] are placed in a three-state condition.
15,41,
65, 91
Power
Supply
Power supply inputs to the core of the device.
5,10,17,21,
26,40,55,60,
67,71,76,
90
Ground
Ground for the device.
Document #: 38-05431 Rev. **
Page 3 of 15
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