CY7C1324F 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1324F Datasheet PDF : 15 Pages
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CY7C1324F
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ..................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range [6, 7]
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature]
0°C to +70°C
–40°C to +85°C
VDD
3.3V
−5%/+10%
VDDQ
3.3V –5%
to VDD
CY7C1324F
Parameter
Description
Test Conditions
Min. Max. Unit
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[6]
Input Load Current
(except ZZ and MODE)
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 3.3V
VDDQ = 3.3V
GND ≤ VI ≤ VDDQ
3.135 3.6
V
3.135 3.6
V
2.4
V
0.4
V
2.0 VDD + 0.3V V
–0.3 0.8
V
−5
5
µA
Input Current of MODE
Input = VSS
–30
µA
Input = VDD
5
µA
Input Current of ZZ
Input = VSS
–5
µA
Input = VDD
30
µA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDD, Output Disabled
–5
5
µA
IOS
Output Short Circuit Current
VDD = Max., VOUT = GND
–300 mA
IDD
VDD Operating Supply Current
VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
f = fMAX= 1/tCYC
8.0-ns cycle, 117 MHz
225 mA
220 mA
ISB1
Automatic CE Power-Down
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
8.0-ns cycle, 117 MHz
90 mA
85 mA
ISB2
Automatic CE Power-Down
Max. VDD, Device Deselected, All speeds
Current—CMOS Inputs
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
40 mA
ISB3
Automatic CE Power-Down
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
Current—CMOS Inputs
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
8.0-ns cycle, 117 MHz
ISB4
Automatic CE Power-Down
Max. VDD, Device Deselected, All speeds
Current—TTL Inputs
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
75 mA
70 mA
45 mA
Notes:
6. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
7. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05431 Rev. **
Page 7 of 15
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