CY7C1324F 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1324F Datasheet PDF : 15 Pages
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CY7C1324F
Thermal Resistance[8]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
TQFP Package
41.83
9.99
Unit
°C/W
°C/W
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 3.3V
Max. Unit
5
pF
5
pF
5
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z0 = 50Ω
3.3V
OUTPUT
RL = 50Ω
5 pF
VL = 1.5V
(a)
INCLUDING
JIG AND
SCOPE
R = 317Ω
R = 351Ω
(b)
VDD
GND
ALL INPUT PULSES
10%
90%
≤ 1 ns
90%
10%
≤ 1 ns
(c)
Switching Characteristics Over the Operating Range[9, 10]
133 MHz
117 MHz
Parameter
tPOWER
Clock
Description
VDD(Typical) to the First Access[11]
Min.
Max.
Min.
Max.
Unit
1
1
ms
tCYC
Clock Cycle Time
tCH
Clock HIGH
tCL
Clock LOW
Output Times
7.5
8.5
ns
2.5
3.0
ns
2.5
3.0
ns
tCDV
Data Output Valid after CLK Rise
6.5
7.5
ns
tDOH
tCLZ
tCHZ
Data Output Hold after CLK Rise
Clock to Low-Z[12, 13, 14]
Clock to High-Z[12, 13, 14]
2.0
2.0
ns
0
0
ns
3.5
3.5
ns
tOEV
tOELZ
tOEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z[12, 13, 14]
OE HIGH to Output High-Z[12, 13, 14]
3.5
3.5
ns
0
0
ns
3.5
3.5
ns
Notes:
8. Tested initially and after any design or process change that may affect these parameters.
9. Timing reference level is 1.5V when VDDQ = 3.3V.
10. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation
can be initiated.
12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
Document #: 38-05431 Rev. **
Page 8 of 15
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