7C1325B-100 데이터 시트보기 (PDF) - Cypress Semiconductor
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7C1325B-100 Datasheet PDF : 17 Pages
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Timing Diagrams
Write Cycle Timing [14, 15]
CY7C1325B
CLK
tADS
ADSP
ADSC
ADV
Single W rite
tCYC
tADH
tADS
tADH
tADVS
tADVH
Burst Write
tCH
Pipelined Write
tCL ADSP ignored with CE1 inactive
ADSC initiated write
Unselected
tAS
ADV Must Be Inactive for ADSP Write
ADD
WD1
WD2
tAH
GW
WE
tWS tWH
tWH
tWS
tCES tCEH
CE1
tCES
CE2
tCEH
CE1 masks ADSP
WD3
Unselected with CE2
CE3
tCES
OE
tCEH
tDH
tDS
Data In High-Z
11aa
2a
2b
= UNDEFINED
2c
2d
3a
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
High-Z
10
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