DD28F032SA 데이터 시트보기 (PDF) - Intel
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DD28F032SA Datasheet PDF : 49 Pages
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DD28F032SA
E
2.1 Lead Descriptions
Symbol
A0
A1–A15
A16–A20
DQ0–DQ7
DQ8–DQ15
CE0#
CEX# =
CE1# or
CE2#
RP#
OE#
WE#
RY/BY#
Type
Name and Function
INPUT
INPUT
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN DRAIN
OUTPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is
high).
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.
A6-15 selects 1 of 1024 rows, and A1-5 selects 16 of 512 columns. These
addresses are latched during data programs.
BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks in each of
the two 28F016SAs. These addresses are latched during data programs,
block erase and lock block operations.
LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
HIGH-BYTE DATA BUS: Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de-
selected or the outputs are disabled.
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. CE0#/CE1# enable/disable the first
28F016SA (16 Mbit No. 1) while CE0#/CE2# enable/disable the second
28F016SA (16 Mbit No. 2). CE0# active low enables chip operation while
CE1# or CE2# select between the first and second device, respectively
CE1# and CE2# must not be active low simultaneously. Reference Table
3.0.
RESET/POWER-DOWN: RP# low places the device in a deep power-
down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or block erase is suspended, or the
device is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE0#/CE1#/CE2# are high), except if a
RY/BY#
Pin Disable command is issued.
8
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