CY7C1340A-66 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1340A-66 Datasheet PDF : 12 Pages
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Pin Configuration
100-pin TQFP
Top View
CY7C1340A
NC 1
DQ17 2
DQ18 3
VCCQ
4
VSSQ
5
DQ19 6
DQ20 7
DQ21
8
DQ22
9
VSSQ
10
VCCQ
11
DQ23
12
DQ24
13
NC 14
VCC
15
NC
16
VSS
17
DQ25
18
DQ26
19
VCCQ
20
VSSQ
21
DQ27
22
DQ28
23
DQ29
24
DQ30 25
VSSQ
26
VCCQ
27
DQ31 28
DQ32 29
NC 30
CY7C1340A
80 NC
79 DQ16
78 DQ15
77
VCCQ
76
VSSQ
75 DQ14
74 DQ13
73 DQ12
72 DQ11
71
VSSQ
70
VCCQ
69 DQ10
68 DQ9
67
VSS
66 NC
65
VCC
64 ZZ
63 DQ8
62 DQ7
61
VCCQ
60
VSSQ
59 DQ6
58 DQ5
57 DQ4
56 DQ3
55
VSSQ
54
VCCQ
53 DQ2
52 DQ1
51 NC
Pin Descriptions
Name
A0–A16
Type
Input-
Synchronous
BW1, BW2,
BW3, BW4
Input-
Synchronous
BWE
GW
Input-
Synchronous
Input-
Synchronous
Description
Addresses: These inputs are registered and must meet the set-up and hold times around
the rising edge of CLK. The burst counter generates internal addresses associated with
A0 and A1, during burst cycle and wait cycle.
Byte Write: A byte Write is LOW for a Write cycle and HIGH for a Read cycle. BW1 controls
DQ1–DQ8. BW2 controls DQ9–DQ16. BW3 controls DQ17–DQ24. BW4 controls
DQ25–DQ32. Data I/O are high-impedance if either of these inputs are LOW, conditioned
by BWE being LOW.
Write Enable: This active LOW input gates byte Write operations and must meet the
set-up and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 32-bit Write to occur independent of the
BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK.
Document #: 38-05153 Rev. *C
Page 3 of 12
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