CY7C135-15(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C135-15
(Rev.:2004)

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

Cypress Semiconductor 

CY7C135

CY7C1342

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port

SRAM with Semaphores

Features

Functional Description

• True Dual-Ported memory cells which allow simulta-

neous reads of the same memory location

• 4K x 8 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

• Low operating power: ICC = 160 mA (max.)

• Fully asynchronous operation

• Automatic power-down

• Semaphores included on the 7C1342 to permit software

handshaking between ports

• Available in 52-pin PLCC

The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8

dual-port static RAMs. The CY7C1342 includes semaphores

that provide a means to allocate portions of the dual-port RAM

or any shared resource. Two ports are provided permitting in-

dependent, asynchronous access for reads and writes to any

location in memory. Application areas include interproces-

sor/multiprocessor designs, communications status buffering,

and dual-port video/graphics memory.

Each port has independent control pins: chip enable (CE),

read or write enable (R/W), and output enable (OE). The

CY7C135 is suited for those systems that do not require

on-chip arbitration or are intolerant of wait states. Therefore,

the user must be aware that simultaneous access to a location

is possible. Semaphores are offered on the CY7C1342 to as-

sist in arbitrating between ports. The semaphore logic is com-

prised of eight shared latches. Only one side can control the

latch (semaphore) at any time. Control of a semaphore indi-

cates that a shared resource is in use. An automatic pow-

er-down feature is controlled independently on each port by a

chip enable (CE) pin or SEM pin (CY7C1342 only).

The CY7C135 and CY7C1342 are available in 52-pin PLCC.

Logic Block Diagram

R/WL

R/WR

CEL

CER

OEL

OER

I/O7L

I/O0L

A11L

A0L

I/O

CONTROL

I/O

CONTROL

ADDRESS

DECODER

MEMORY

ARRAY

ADDRESS

DECODER

I/O7R

I/O0R

A11R

A0R

(7C1342 only) SEM

L

CEL

OEL

R/WL

SEMAPHORE

ARBITRATION

(7C1342 only)

CER

OER

R/WR

(7C1342 only)

R

SEM

1342–1

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-06038 Rev. *B

Revised June 22, 2004

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