CY7C150 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C150 Datasheet PDF : 11 Pages
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CY7C150
Switching Characteristics Over the Operating Range[2,5]
7C150−10 7C150−12 7C150−15 7C150−25 7C150−35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
tAA
tOHA
Read Cycle Time
Address to Data Valid
Output Hold from Address
Change
10
12
15
25
35
ns
10
12
15
25
35 ns
2
2
2
2
2
ns
tACS
tLZCS
tHZCS
CS LOW to Data Valid
CS LOW to Low Z[6]
CS HIGH to High Z[6,7]
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[6]
tHZOE
OE HIGH to High Z[6,7]
WRITE CYCLE[8]
8
10
12
15
20 ns
0
0
0
0
0
ns
6
8
11
20
25 ns
6
8
10
15
20 ns
0
0
0
0
0
ns
6
8
9
20
25 ns
tWC
Write Cycle Time
tSCS
CS LOW to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tPWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[6,7]
RESET CYCLE
10
12
15
25
35
ns
6
8
11
15
20
ns
8
10
13
20
30
ns
2
2
2
5
5
ns
2
2
2
5
5
ns
6
8
11
15
20
ns
6
8
11
15
20
ns
2
2
2
5
5
ns
0
0
0
0
0
ns
6
8
12
20
25 ns
tRRC
Reset Cycle Time
20
24
30
50
70
ns
tSAR
Address Valid to Beginning of
0
0
0
0
0
ns
Reset
tSWER
Write Enable HIGH to Beginning 0
0
0
0
0
ns
of Reset
tSCSR
Chip Select LOW to Beginning of 0
0
0
0
0
ns
Reset
tPRS
Reset Pulse Width
10
12
15
20
30
ns
tHCSR
Chip Select Hold After End of
0
0
0
0
0
ns
Reset
tHWER
Write Enable Hold After End of
8
Reset
12
15
30
40
ns
tHAR
tLZRS
tHZRS
Address Hold After End of Reset 10
12
15
30
40
ns
Reset HIGH to Output in Low Z[6] 0
0
0
0
0
ns
Reset LOW to Output in
High Z[6,7]
6
8
12
20
25 ns
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
7. tHZCS, tHZOE, tHZR, and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write.
Document #: 38-05024 Rev. *A
Page 3 of 11
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