Switching Waveforms (continued)
Write Cycle No2. (CS Controlled) [8,12]
ADDRESS
CE
WE
tSA
tAW
DATA IN
DATA I/O
DATA UNDEFINED
tWC
tSCS
tHA
tPWE
tSD
tHD
DATA IN VALID
tHZWE
HIGH IMPEDANCE
Reset Cycle [13]
ADDRESS
WE
tSAR
tSWER
tRRC
tHAR
tHWER
CY7C150
C150-8
CS
RESET
DATA I/O
tSCSR
tHCSR
tPRS
tHZRS
tLZRS
HIGH
IMPEDANCE
OUTPUT VALID ZERO
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state.
13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.
C150-9
Document #: 38-05024 Rev. *A
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