CY7C186-35PC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C186-35PC Datasheet PDF : 9 Pages
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CY7C186
AC Test Loads and Waveforms
5V
OUTPUT
R1 481Ω
5V
OUTPUT
R1 481Ω
30 pF
INCLUDING
JIG AND
SCOPE (a)
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE (b)
R2
255Ω
3.0V
GND 10%
≤ 5 ns
ALL INPUT PULSES
90%
90%
10%
≤ 5 ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics Over the Operating Range[5]
7C186-20
7C186-25
7C186-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE1
CE1 LOW to Data Valid
tACE2
CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE1
OE LOW to Low Z
OE HIGH to High Z[6]
CE1 LOW to Low Z[7]
tLZCE2
tHZCE
CE2 HIGH to Low Z
CE1 HIGH to High Z[6, 7]
CE2 LOW to High Z
tPU
CE1 LOW to Power-Up
tPD
CE1 HIGH to Power-Down
WRITE CYCLE[8]
20
25
35
ns
20
25
35
ns
5
5
5
ns
20
25
35
ns
20
25
35
ns
9
12
15
ns
3
3
3
ns
8
10
10
ns
5
5
5
ns
3
3
3
ns
8
10
10
ns
0
0
0
ns
20
20
20
ns
tWC
Write Cycle Time
20
25
35
ns
tSCE1
CE1 LOW to Write End
15
20
20
ns
tSCE2
CE2 HIGH to Write End
15
20
20
ns
tAW
Address Set-Up to Write End
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
15
15
20
ns
tSD
Data Set-Up to Write End
10
10
12
ns
tHD
tHZWE
Data Hold from Write End
WE LOW to High Z[6]
0
0
0
ns
7
7
8
ns
tLZWE
WE HIGH to Low Z
5
5
5
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All signals must be active to initiate a write, and any
signal can terminate a write by going inactive. The data input set-up and hold timing should be referenced to the trailing edge of the signal that terminates the
write.
Document #: 38-05280 Rev. **
Page 3 of 9
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