CY7C187 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
제조사
CY7C187 Datasheet PDF : 9 Pages
| |||
CY7C187
Switching Characteristics Over the Operating Range[5]
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
tLZCE
tHZCE
CE LOW to Data Valid
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Down
WRITE CYCLE[8]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z[7]
-15
Min. Max.
15
15
3
15
3
8
0
15
15
12
12
0
0
12
10
0
5
7
-25
Min. Max.
25
25
5
25
5
10
0
20
20
20
20
0
0
15
10
0
5
7
-35
Min. Max.
35
35
5
35
5
15
0
20
25
25
25
0
0
20
15
0
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
C187–6
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
7. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = VIL.
Document #: 38-05044 Rev. *A
Page 3 of 9
[+] Feedback
Share Link: 