CY7C188 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C188 Datasheet PDF : 7 Pages
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AC Test Loads and Waveforms[4, 5]
5V
OUTPUT
R1 481Ω
5V
OUTPUT
R1 481Ω
30 pF
INCLUDING
JIGAND
SCOPE
R2
255Ω
(a)
5 pF
R2
255Ω
INCLUDING
JIGAND
SCOPE (b)
C188–3
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
CY7C188
3.0V
10%
GND
≤ 3 ns
ALLINPUTPULSES
90%
90%
10%
≤ 3 ns
C188–4
Switching Characteristics Over the Operating Range[2, 4]
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW or CE2 HIGH to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[5,6]
CE1 LOW or CE2 HIGH to Low Z[6]
CE1 HIGH or CE2 LOW to High Z[5, 6]
tPU
CE1 LOW or CE2 HIGH to Power-Up
tPD
CE1 HIGH or CE2 LOW to Power-Down
WRITE CYCLE[7, 8]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
CE1 LOW or CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[5]
WE HIGH to Low Z[5, 6]
–15
–20
Min.
Max.
Min.
Max.
Unit
15
20
ns
15
20
ns
3
3
ns
15
20
ns
7
9
ns
0
0
ns
7
9
ns
3
3
ns
7
9
ns
0
0
ns
15
20
ns
15
20
ns
10
15
ns
10
15
ns
0
0
ns
0
0
ns
10
15
ns
8
10
ns
0
0
ns
0
7
0
7
ns
3
3
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE1, LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write and any
signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
8. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05053 Rev. *A
Page 3 of 7
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