CY7C188 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C188 Datasheet PDF : 7 Pages
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CY7C188
Switching Waveforms
Read Cycle No. 1[9,10]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
Read Cycle No. 2 (Chip-Enable Controlled)[10,11,12]
CE1
OE
DATA OUT
VCC
SUPPLY
CURRENT
tRC
tACE
tDOE
tLZOE
HIGH IMPEDANCE
tLZCE
tPU
50%
Write Cycle No. 1 (WE Controlled)[7,12,13,14]
tWC
ADDRESS
DATA VALID
CE1
WE
tAW
tSA
tPWE
OE
DATA I/O
NOTE 15
tHZOE
tSD
DATA IN VALID
Notes:
9. Device is continuously selected. OE, CE = VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
12. Timing parameters are the same for all chip enable signals (CE1 and CE2), so only the timing for CE1 is shown.
13. Data I/O is high impedance if OE = VIH.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in the output state and input signals should not be applied.
DATA VALID
C188–5
tHZOE
tHZCE
HIGH
IMPEDANCE
tPD
50%
ICC
ISB
C188–6
tHA
tHD
C188–7
Document #: 38-05053 Rev. *A
Page 4 of 7
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