CY7C199D(2007) 데이터 시트보기 (PDF) - Cypress Semiconductor
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| CY7C199D Datasheet PDF : 0 Pages | |||
Switching Characteristics (Over the Operating Range) [5]
Parameter
Read Cycle
tpower [6]
tRC
tAA
tOHA
tACE
tDOE
tLZOE [7]
tHZOE [7, 8]
tLZCE [7]
tHZCE [7, 8]
tPU [9]
tPD [9]
Write Cycle [10, 11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE [7]
tLZWE [7, 8]
Description
VCC(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
CY7C199D
7C199D-10
Min
Max
Unit
100
µs
10
ns
10
ns
3
ns
10
ns
5
ns
0
ns
5
ns
3
ns
5
ns
0
ns
10
ns
10
ns
7
ns
7
ns
0
ns
0
ns
7
ns
5
ns
0
ns
6
ns
3
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of
the specified IOL/IOH and 30-pF load capacitance.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of “AC Test Loads and Waveforms [4]” on page 4. Transition is measured ±200 mV from steady-state voltage.
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD .
Document #: 38-05471 Rev. *D
Page 5 of 10
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