CY7C1335-100AC(1999) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1335-100AC Datasheet PDF : 15 Pages
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CY7C1335
Linear Burst Sequence
First
Address
Second
Address
Third
Address
A[1:0]
00
A[1:0]
01
A[1:0]
10
01
10
11
10
11
00
11
00
01
Fourth
Address
A[1:0]
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Snooze mode
standby current
ZZ > VDD − 0.2V
3
mA
tZZS
Device operation to ZZ > VDD − 0.2V
ZZ
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
5
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