CY7C1335 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1335 Datasheet PDF : 15 Pages
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PRELIMINARY
CY7C1335
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (TCO) is 5.5 ns (100
MHz device). A two-bit on-chip wraparound burst counter cap-
tures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
The CY7C1335 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order is user selectable, and is de-
termined by sampling the MODE input. Accesses can be ini-
tiated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[0-3]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs
(A0-A14) is stored into the address advancement logic and the
Address Register while being presented to the memory core.
The corresponding data is allowed to propagate to the input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 5.5 ns (100 MHz device) if OE is active
low. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address pre-
sented to A0-A14 is loaded into the address register and the
address advancement logic while being delivered to the RAM
core. The write signals (GW, BWE and BW0-BW3) and ADV
inputs are ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise,
the data presented to the DQ0-DQ31 inputs is written into the
corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW[3:0] signals. The CY7C1335 provides byte write capability
that is described in the write cycle description table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW0 - BW3) input will selectively write to only the de-
sired bytes. Bytes not selected during a byte write operation
will remain unaltered. A Synchronous self-timed write mecha-
nism has been provided to simplify the write operations.
Because the CY7C1335 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ0-DQ31 inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ0-DQ31 are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW0 - BW3) are asserted active to conduct a write
to the desired byte(s). ADSC triggered write accesses require
a single clock cycle to complete. The address presented to
A0-A14 is loaded into the address register and the address
advancement logic while being delivered to the RAM core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQ0-DQ31 is written into
the corresponding address location in the RAM core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain unal-
tered. A Synchronous self-timed write mechanism has been
provided to simplify the write operations.
Because the CY7C1335 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ0-DQ31 inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ0-DQ31 are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1335 provides a two-bit wraparound counter, fed by
A0 and A1, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
00
11
10
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
10
01
00
4
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