CY7C4261-15(2003) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C4261-15
(Rev.:2003)

16K/32K x 9 Deep Sync FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Programmable Almost Empty Flag Timing

tCLKH

tCLKL

WCLK

WEN1

tENS tENH

CY7C4261

CY7C4271

WEN2

(if applicable)

PAE

RCLK

tENS tENH

tESKEW2[21]

Note

22

tPAE

REN1,

REN2

Programmable Almost Full Flag Timing

tCLKH

tCLKL

WCLK

WEN1

tENS tENH

Note

24

N + 1 WORDS

IN FIFO

tENS

tENS tENH

Note 23 tPAE

WEN2

(if applicable)

PAF

RCLK

tENS tENH

FULL − (M+1)WORDS

IN FIFO

Note

25

tPAF

FULL − MWORDS

IN FIFO [26]

tSKEW2 [27]

tPAF

tENS

tENS tENH

REN1,

REN2

Note:

21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising

RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.

22. PAE offset= n.

23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW

24. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.

25. PAF offset = m.

26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271.

27. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and

the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.

Document #: 38-06015 Rev. *B

Page 11 of 18

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