WRITE CYCLE 2 (E Controlled, See Note 1)
– 12
– 15
– 20
– 25
Parameter
Symbol Min Max Min Max Min Max Min Max
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Enable to End of Write
tAVAV
12
—
15
—
20
—
25
—
tAVEL
0
—
0
—
0
—
0
—
tAVEH
10
—
12
—
15
—
20
—
tELEH,
9
tELWH
—
10
—
12
—
15
—
Data Valid to End of Write
tDVEH
6
—
7
—
8
—
10
—
Data Hold Time
tEHDX
0
—
0
—
0
—
0
—
Write Recovery Time
tEHAX
0
—
0
—
0
—
0
—
NOTES:
1. A write occurs during the overlap of E low and W low.
2. All timings are referenced from the last valid address to the first transitioning address.
3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state.
4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state.
Unit Notes
ns
ns
ns
ns
3,4
ns
ns
ns
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
WRITE CYCLE 2 (E Controlled, See Note 1)
tAVAV
tAVEL
tAVEH
tWLEH
tELEH
tELWH
tDVEH
DATA VALID
tEHAX
tEHDX
Q (DATA OUT)
HIGH Z
MCM6206BB
6
MOTOROLA FAST SRAM