CY62256 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY62256 Datasheet PDF : 12 Pages
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CY62256
Features
• 4.5V–5.5V Operation
• Low active power (70 ns, LL version)
— 275 mW (max.)
• Low standby power (70 ns, LL version)
— 28 µW (max.)
• 55, 70 ns access time
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62256 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
32Kx8 Static RAM
output enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power consump-
tion by 99.9% when deselected. The CY62256 is in the stan-
dard 450-mil-wide (300-mil body width) SOIC, TSOP, and
600-mil PDIP packages.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
Pin Configurations
A10
A9
A8
A7
A6
A5
A4
A3
A2
CE
WE
OE
C62256–1
A11
A10
A9
A8
A7
A6
A5
VCC
WE
A4
A3
A2
A1
OE
INPUTBUFFER
512x512
ARRAY
COLUMN
DECODER
POWER
DOWN
7
6
5
4
3
TSOP I
2
Reverse Pinout
1
28
Top View
27
(not to scale)
26
25
24
23
22
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
8 A12
9 A13
10 A14
11 I/O0
12 I/O1
13 I/O2
14 GND
15 I/O3
16 I/O4
17 I/O5
18 I/O6
19 I/O7
20 CE
21 A0
OE 22
A1
23
A2
24
A3
25
A4
26
WE
27
VCAC5
28
1
A6
2
A7
3
A8
4
A9
5
A10
6
A11
7
C62256–4
SOIC/DIP
Top View
A5 1
A6 2
A7 3
A8 4
A9 5
A10 6
A11 7
A12 8
A13 9
A14 10
I/O0 11
I/O1 12
I/O2 13
GND 14
28 VCC
27 WE
26 A4
25 A3
24 A2
23 A1
22 OE
21 A0
20 CE
19
18
I/O7
I/O6
17 I/O5
16 I/O4
15 I/O3
C62256–2
TSOP I
Top View
(not to scale)
21 A0
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 GND
13 I/O2
12 I/O1
11 I/O0
10 A14
9 A13
8 A12
C62256–3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 1996 – Revised November 26, 1997
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