CY8C41223 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY8C41223

Linear Power PSoC™ Devices

Cypress Semiconductor 

PRELIMINARY

CY8C41123 and CY8C41223

7.2 Register Map Bank 0 Table: User Space

Name

Addr

(0,Hex)

Access

Name

Addr

(0,Hex)

Access

PRT0DR

00

RW

40

PRT0IE

01

RW

41

PRT0GS

02

RW

42

PRT0DM2

03

RW

43

PRT1DR

04

RW

44

PRT1IE

05

RW

45

PRT1GS

06

RW

46

PRT1DM2

07

RW

47

HVP2_DR

08

RW

48

09

49

0A

4A

0B

4B

0C

4C

0D

4D

0E

4E

0F

4F

10

50

11

51

12

52

13

53

14

54

15

55

16

56

17

57

18

58

19

59

1A

5A

1B

5B

1C

5C

1D

5D

1E

5E

1F

5F

DBC00DR0

20

R

AC0_MUX

60

RW

DBC00DR1

21

W

AC0_CR0

61

RW

DBC00DR2

22

RW

AC0_CR1

62

RW

DBC00CR0

23

RW

AC0_CR2

63

RW

DBC01DR0

24

R

AC0_MSP

64

RW

DBC01DR1

25

W

AC0_LSP

65

RW

DBC01DR2

26

RW

AC0_MSR

66

RW

DBC01CR0

27

RW

AC0_LSR

67

RW

DBD02DR0

28

R

AC0_CC

68

#

DBD02DR1

29

W

69

DBD02DR2

2A

RW

6A

DBD02CR0

2B

RW

6B

DBD03DR0

2C

R

TMP_DR0

6C

RW

DBD03DR1

2D

W

TMP_DR1

6D

RW

DBD03DR2

2E

RW

TMP_DR2

6E

RW

DBD03CR0

2F

RW

TMP_DR3

6F

RW

30

CMP_SYN

70

RW

31

CMP_LFN0

71

RW

32

72

33

CMP_LMD

73

RW

34

CMP_CDS

74

RW

35

CMP_CIS

75

RW

36

CMP_RDC

76

RW

37

CMP_GOEN0 77

RW

38

78

39

CMP_CLK

79

RW

3A

CMP_CR

7A

RW

3B

CMP_SRC

7B

RW

3C

CMP_MUX0

7C

RW

3D

CMP_MUX1

7D

RW

3E

7E

3F

7F

Blank fields are Reserved and should not be accessed.

Name

ASC00CR0

ASC00CR1

ASC00CR2

ASC00CR3

ASC01CR0

ASC01CR1

ASC01CR2

ASC01CR3

PWR0_CR

PWR1_CR

AA_REF

VDAC_CR

VDAC_DR0

VDAC_DR1

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDI0GF

Document 001-00360 Rev. *A

Addr

(0,Hex)

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

Access

Name

RW

RW

RW

RW

IDAC_D

RW

P0_MUX

RW

P1_MUX

RW

RW

I2C_CFG

I2C_SCR

I2C_DR

I2C_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

RW

INT_MSK0

RW

INT_MSK1

INT_VC

RES_WDT

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

CPU_F

CPU_SCR2

CPU_SCR1

CPU_SCR0

Addr

(0,Hex)

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

Access

RW

RW

RW

RW

#

RW

#

RW

RW

RW

RW

RW

RW

RW

RW

RC

W

RL

RSW

#

#

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