CY8C41223 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY8C41223

Linear Power PSoC™ Devices

Cypress Semiconductor 

PRELIMINARY

CY8C41123 and CY8C41223

5.2 Linear Battery Charger

A battery charger is constant current and constant voltage power supply. At different points in a charging cycle a Lithium Ion

battery requires a constant current or a constant voltage to be applied. The CY8C41x23 Linear Power PSoC can be configured

as a constant voltage or constant current linear supply. In this configuration, the HVdd voltage is high enough to drive one or more

battery in series. Lithium Ion batteries have a fully charged voltage of 4.2V. With the two-cell configuration in Figure 5-2, HVdd

would have to be at least 8.4V (plus allowance for voltage losses in the FET and the current sense resistor, RISENSE). The HVdd

voltage is converted to 5V by the internal Low Drop-Out Regulator for use by the Power PSoC Core.

To maintain constant voltage, the gate of the External PFET is controlled by the GDO0 pin and driven in a linear mode. The voltage

at the top of the load, connected to VS0, is attenuated by the internal resistive element, Atten0. The voltage out of the attenuator

is fed into the positive terminal of an amplifier configured as a voltage follower. The amplifier's negative input is connected to the

output of the voltage DAC, VDAC0. This creates a feedback loop that maintains the VS0 node at a voltage proportional to the

VDAC0 setting. The Atten0 output is also connected to the ADC so the control software can monitor the output voltage. The

accuracy of the ADC and the control loop are better than 0.75%. Meeting high accuracy is critical to Lithium Ion batteries.

To maintain constant current, the voltage across the RISENSE resistor is routed through pin P0[4] and AMuxBus0 to the ADC

where it is monitored. The control software adjusts the VDAC0 setting, based on current sense measurements, to achieve the

desired current through the load. The current sense voltage is also connected to the positive input of COMP0. The negative input

of COMP0 is controlled by the output of ODAC0. If the current sense voltage exceeds the ODAC0 setting, the output of the

comparator will be latched high. This acts as an over-current detection circuit, which can be cleared by the control software. The

output of the comparator, COMP0, can be connected to the enable of the GDO0 output driver. This configures the Power PSoC

so that an over-current condition will shut off the External PFET.

5.2.1 Resources

This application could connect the RISENSE resistor to any of the GPIO pins (P0[7:0] and P1[1:0]). The Linear Power PSoC still

has all of its digital resources, half of the high voltage resources, one VDAC, two IDACs, seven of the analog multiplexer channels

to the ADC, and over 90% of the CPU available to implement the battery charging algorithm and other tasks.

HVdd

HVdd

GDO1

VS1

P0[7]

P0[5]

P0[3]

P0[1]

P1[1]

LowDrop-Out

Reg ul ator

InternalVdd

ANALOG and HIGH VOLTAGE

SECTIONS

ODAC1

VDAC1

VBG

ODAC0

VDAC0

VDAC1 IBIAS VDAC0

Analog to

D ig ital

Convertor

Atten1

AMuxBus3

AMuxBus1

Atten0

AMuxBus2

AMuxBus0

COMP1

ODAC1

ODAC0

COMP0

GDO0

VS0

P0[6]

P0[4]

P0[2]

P0[0]

P1[0]

HVdd

Ext.

PFET

RISENSE

Figure 5-2. Linear Battery Charger

Document 001-00360 Rev. *A

Page 6 of 36

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