LHF32KZ5 데이터 시트보기 (PDF) - Sharp Electronics

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LHF32KZ5

Flash Memory 32M (× 8 or ×16)

Sharp Electronics 

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LHF32KZ5

7

2 PRINCIPLES OF OPERATION

The LH28F320SKTD-L70 Dual Work Flash memory

includes an on-chip WSM to manage block erase,

bank erase, (multi) word/byte write and block lock-bit

configuration functions. It allows for: 100% TTL-level

control inputs, fixed power supplies during block

erase, bank erase, (multi) word/byte write and block

lock-bit configuration, and minimal processor

overhead with RAM-Like interface timings.

After initial device power-up or return from deep

power-down mode (see Bus Operations), the device

defaults to read array mode. Manipulation of external

memory control pins allow array read, standby, and

output disable operations.

Status register, query structure and identifier codes

can be accessed through the CUI independent of the

VPP voltage. High voltage on VPP enables successful

block erase, bank erase, (multi) word/byte write and

block lock-bit configuration. All functions associated

with altering memory contentsblock erase, bank

erase, (multi) word/byte write and block lock-bit

configuration, status, query and identifier codesare

accessed via the CUI and verified through the status

register.

Commands are written using standard

microprocessor write timings. The CUI contents serve

as input to the WSM, which controls the block erase,

bank erase, (multi) word/byte write and block lock-bit

configuration. The internal algorithms are regulated

by the WSM, including pulse repetition, internal

verification, and margining of data. Addresses and

data are internally latch during write cycles. Writing

the appropriate command outputs array data,

accesses the identifier codes, outputs query structure

or outputs status register data.

Interface software that initiates and polls progress of

block erase, bank erase, (multi) word/byte write and

block lock-bit configuration can be stored in any

block. This code is copied to and executed from

system RAM during flash memory updates. After

successful completion, reads are again possible via

the Read Array command. Block erase suspend

allows system software to suspend a block erase to

read or write data from any other block. Write

suspend allows system software to suspend a (multi)

word/byte write to read data from any other flash

memory array location.

2.1 Data Protection

Depending on the application, the system designer

may choose to make the VPP power supply

switchable (available only when block erase, bank

erase, (multi) word/byte write and block lock-bit

configuration are required) or hardwired to VPPH1/2/3.

The device accommodates either design practice and

encourages optimization of the processor-memory

interface.

When VPP≤VPPLK, memory contents cannot be

altered. The CUI, with multi-step block erase, bank

erase, (multi) word/byte write and block lock-bit

configuration command sequences, provides

protection from unwanted operations even when high

voltage is applied to VPP. All write functions are

disabled when VCC is below the write lockout voltage

VLKO or when RP# is at VIL. The device’s block

locking capability provides additional protection from

inadvertent code or data alteration by gating block

erase, bank erase and (multi) word/byte write

operations.

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