NT7501H-BDT 데이터 시트보기 (PDF) - Novatek Microelectronics
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NT7501H-BDT Datasheet PDF : 38 Pages
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NT7501
Display Timing Generator
This section explains how the display timing generator circuit operates.
Signal Generation to Line Counter and Display Data Latch Circuit
The display clock (CL) generates a clock to the line counter and a latch signal to the display data latch circuit.
The line address of the display RAM is generated in synchronization with the display clock. 100-bit display data is latched by the
display data latch circuit in synchronization with the display clock and output to the segment LCD drive output pad.
The display data is read to the LCD drive circuit completely independent of access to the display data RAM from the
microprocessor.
LCD AC Signal (FR) Generation
The display clock generates an LCD AC signal (FR). The FR causes the LCD drive circuit to generate a AC drive waveform.
It generates a 2-frame AC drive waveform.
When the NT7501 is operated in slave mode on the assumption of multi-chip, the FR pad and CL pad become input pads.
Common Timing Signal Generation
The display clock generates an internal common timing signal and a start signal (DYO) to the common driver. A display clock
resulting from frequency division of an oscillation clock is output from the CL pad.
When an AC signal (FR) is switched, a high pulse is output as a DYO output at the turning edge of the previous display clock.
Refer to Figure 5. The DYO output is output only in master mode.
When the NT7501 is used for multi-chip, the slave requires to receive the FR, CL, DOF signals from the master.
Table 4 shows the FR, CL, DYO and DOF status.
Table 4.
Model
Operation mode FR
CL
DYO
NT7501
Master
Slave
Output
Input
Output
Input
Output
HZ
HZ denotes a high-impedance status
Example of NT7501 1/33 duty (Dual-frame AC driver waveforms)
DOF
Output
Input
32 33 1
2345
6
28 29 30 31 32 33 1 2 3 4 5
CL
FR
DYO
V0
COM0
V1
V4
VSS
V0
COM1
V1
V4
VSS
RAM
data
V0
SEGn
V2
V3
VSS
Figure 5.
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