PCF8531U 데이터 시트보기 (PDF) - Philips Electronics
부품명
상세내역
제조사
PCF8531U Datasheet PDF : 44 Pages
| |||
Philips Semiconductors
34 × 128 pixel matrix driver
Product specification
PCF8531
SYMBOL
PAD
DESCRIPTION
C0 to C127
R33
R31
R29
R27
R25
R23
R21
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
104 to 231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
LCD column driver outputs
LCD row driver output; icon row
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
Notes
1. If the on-chip oscillator is used this input must be connected to VDD1.
2. If the internal VLCD generation is used, VLCDOUT, VLCDIN and VLCDSENSE must be connected together.
3. If in the application an external VLCD is used, then the VLCDOUT pin must be left open-circuit, otherwise the chip will
be damaged.
4. If only the internal Power-on reset is used this input must be connected to VDD1.
5. VDD1 is for the logic supply, VDD2, and VDD3 are for the voltage multiplier. For split power supplies VDD2 and VDD3
must be connected together. If only one supply voltage is available VDD1, VDD2 and VDD3 must be connected together.
6. Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes fully
I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in
Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDACK pad to the
system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin
Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the PCF8531 will not be able to create
a valid logic 0 level. By splitting the SDA input from the SDACK output the device could be used in a mode that
ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to
minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level.
7. If ENR is connected to VSS Power-on reset is disabled; to enable Power-on reset ENR should be connected to VDD1.
8. In the application this input must be connected to VSS.
9. VSS1 and VSS2 must be connected together.
10. In the application T2 must be left open-circuit.
1999 Aug 10
6
Share Link: 