DM74S299N 데이터 시트보기 (PDF) - Fairchild Semiconductor
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DM74S299N Datasheet PDF : 5 Pages
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Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
VOH
HIGH Level
VCC = Min, IOH = Max
QA thru QH
2.4
Output Voltage
VIL = Max, VIH = Min
QA′, QH′
2.7
VOL
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
II
Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
IIH
HIGH Level
VCC = Max
A thru H,
Input Current
VI = 2.7V
S0, S1
Any Other
IIL
LOW Level
Input Current
VCC = Max
VI = 0.5V
Clock, Clear
S0, S1
Other
IOZH
Off-State Output Current with
VCC = Max, VO = 2.4V
HIGH Level Output Voltage
VIH = Min, VIL = Max
Applied (QA thru QH)
IOZL
Off-State Output Current with
VCC = Max, VO = 0.5V
LOW Level Output Voltage
VIH = Min, VIL = Max
Applied (QA thru QH)
IOS
Short Circuit Output
VCC = Max
−40
Current (QA thru QH)
(Note 10)
Short Circuit Output
VCC = Max
−20
Current (QA′, QH′)
(Note 10)
ICC
Supply Current
VCC = Max
Note 8: TA = 25°C and VCC = 5V.
Note 9: All typicals are at VCC = 5V, TA = 25°C.
Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Typ
(Note 8)
3.2
3.4
140
Max
−1.2
0.5
1
100
50
−2
−0.5
−0.25
100
−250
−100
−100
225
Switching Characteristics
at VCC = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
fMAX
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output (Note 12)
Propagation Delay Time
HIGH-to-LOW Level Output (Note 12)
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output (Note 12)
Propagation Delay Time
HIGH-to-LOW Level Output
To (Output)
(Note 13)
Clock to QA′ or QH′
Clock to QA′ or QH′
Clock to QA thru QH
Clock to QA thru QH
Clear to QA′ or QH′
Clear to QA thru QH
tPZH
Output Enable Time to HIGH Level Output
G1, G2 to QA thru QH
tPZL
Output Enable Time to LOW Level Output
G1, G2 to QA thru QH
tPHZ
Output Disable Time to HIGH Level Output (Note 11) G1, G2 to QA thru QH
tPLZ
Output Disable Time to LOW Level Output (Note 11)
Note 11: CL = 5 pF.
Note 12: RL = 1KΩ for delays measured to QA′ and QH′.
Note 13: For testing fMAX all outputs are loaded simultaneously.
G1, G2 to QA thru QH
RL = 280Ω (Note 12)
CL = 15 pF
CL = 50 pF
Min
Max
Min
Max
50
40
20
22
20
23
21
21
21
24
24
18
18
12
12
Units
V
V
V
mA
µA
mA
µA
µA
mA
mA
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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