DM9010(2005) 데이터 시트보기 (PDF) - Davicom Semiconductor, Inc.

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DM9010
(Rev.:2005)

10/100 Mbps Single Chip Ethernet Controller with General Processor Interface

Davicom Semiconductor, Inc. 

DM9010

Single Chip Ethernet Controller with General Processor Interface

6.46 INTERRUPT STATUS REGISTER (FEH) ......................................................................................................................... 28

6.47 INTERRUPT MASK REGISTER (FFH)............................................................................................................................ 28

7. EEPROM FORMAT........................................................................................................................................................ 29

8. MII REGISTER DESCRIPTION ................................................................................................................................... 30

8.1 BASIC MODE CONTROL REGISTER (BMCR) - 00 .......................................................................................................... 31

8.2 BASIC MODE STATUS REGISTER (BMSR) - 01.............................................................................................................. 32

8.3 PHY ID IDENTIFIER REGISTER #1 (PHYID1) - 02 ........................................................................................................ 34

8.4 PHY ID IDENTIFIER REGISTER #2 (PHYID2) - 03 ........................................................................................................ 34

8.5 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) - 04 ................................................................................... 34

8.6 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) – 05................................................................... 35

8.7 AUTO-NEGOTIATION EXPANSION REGISTER (ANER)- 06 ............................................................................................. 36

8.8 DAVICOM SPECIFIED CONFIGURATION REGISTER (DSCR) - 16 ................................................................................. 37

8.9 DAVICOM SPECIFIED CONFIGURATION AND STATUS REGISTER (DSCSR) - 17.......................................................... 38

8.10 10BASE-T CONFIGURATION/STATUS (10BTCSR) - 18.............................................................................................. 39

8.11 POWER DOWN CONTROL REGISTER (PWDOR) - 19 ................................................................................................... 40

8.12 (SPECIFIED CONFIG) REGISTER – 20 ............................................................................................................................ 41

9. FUNCTIONAL DESCRIPTION..................................................................................................................................... 42

9.1 HOST INTERFACE .......................................................................................................................................................... 42

9.2 DIRECT MEMORY ACCESS CONTROL............................................................................................................................ 42

9.3 PACKET TRANSMISSION................................................................................................................................................ 42

9.4 PACKET RECEPTION...................................................................................................................................................... 42

9.5 100BASE-TX OPERATION............................................................................................................................................. 43

9.5.1 4B5B Encoder ...................................................................................................................................................... 43

9.5.2 Scrambler ............................................................................................................................................................. 43

9.5.3 Parallel to Serial Converter................................................................................................................................. 43

9.5.4 NRZ to NRZI Encoder .......................................................................................................................................... 43

9.5.5 MLT-3 Converter ................................................................................................................................................. 43

9.5.6 MLT-3 Driver....................................................................................................................................................... 43

9.5.7 4B5B Code Group ................................................................................................................................................ 44

9.6 100BASE-TX RECEIVER ............................................................................................................................................... 45

9.6.1 Signal Detect ........................................................................................................................................................ 45

9.6.2 Adaptive Equalization .......................................................................................................................................... 45

Preliminary

4

Version: DM9010-DS-P03

Apr. 28, 2005

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