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DS1040-B50 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1040-B50
Dallas
Dallas Semiconductor -> Maxim Integrated Dallas
DS1040-B50 Datasheet PDF : 6 Pages
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POWER-UP TIMING DIAGRAM Figure 3
DS1040
TEST CIRCUIT Figure 4
TERMINOLOGY
Period: The time elapsed between the leading edge of the first trigger pulse and the leading edge of the
following trigger pulse.
tWIH , WIL , WO (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge
and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the
leading edge.
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