DS1205S 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1205S

MultiKey Chip

Dallas Semiconductor -> Maxim Integrated 

DS1205S

EQUIVALENT CIRCUIT Figure 15

RX

TX

100 ohm

MOSFET

BUS MASTER OPEN DRAIN CIRCUIT

Figure 16A

VDD

Microcontroller

VDD

DS5000 or 8051 equivalent

Open Drain

Port Pin

5K ohms

RX

TX

To data

connection

of DS1205S

BUS MASTER STANDARD TTL CIRCUIT

Figure 16B

VDD

Microcontroller

TTL–Equivalent

Port Pins

Rx

To data

connection

of DS1205S

Transaction Sequence

The protocol for accessing the DS1205S is as follows:

Reset

Presence Detect

1-wire Command Word

Device Command Word

Transaction/Data

CRC

Reset/Presence Detect - All transactions on the 1-wire

bus begin with the reset sequence. The reset sequence

is started by holding the data line low for 560 µS. The

DS1205S is designed to be held in the reset state when-

ever it is not connected to the bus. When it is connected

to the bus, the data line is pulled high, the part is taken

out of reset, and the part is ready to issue the presence

detect.

After detecting a high state on the data line, the

DS1205S waits 15 µS minimum and issues its presence

detect. This presence detect is a low-going pulse that

last 70 µS. This response to the reset pulse lets the bus

master know that the DS1205S is on the bus and is

ready to operate. The presence detect helps the bus

master to discriminate the communication signals from

noise as the DS1205S is taken on and off the bus. Refer

to the timing diagram in Figure 17.

After the DS1205S has responded to the reset pulse

with a presence detect, the bus master drives the bus to

the idle state for a minimum of 1 µS. The 1 µS interval is

like a frame sync. After each bit is transmitted on the

bus, there is a frame strobe to sync up for the next trans-

mission. Refer to Figure 17.

Tx

5K ohms

021798 10/17

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