DS1808Z-050-TR 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1808Z-050-TR

Dual Log Digital Potentiometer

Dallas Semiconductor -> Maxim Integrated 

2-WIRE SERIAL PROTOCOL

DS1808

The following bus protocol has been defined:

§ Data transfer may be initiated only when the bus is not busy.

§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in the

data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain high.

Start data transfer: A change in the state of the data line from high to low while the clock is high

defines a start condition.

Stop data transfer: A change in the state of the data line from low to high while the clock line is high

defines the stop condition.

Data valid: The state of the data line represents valid data when, after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line can be changed during

the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how

data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of

data transfer are possible.

Each data transfer is initiated with a start condition and terminated with a stop condition. The number of

data bytes transferred between start and stop conditions is not limited and is determined by the master

device. The information is transferred byte-wise and each receiver acknowledges with a 9th bit.

Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are

defined. The DS1808 works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an “acknowledge” after the

reception of each byte. The master device must generate an extra clock pulse that is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into account. A master must signal an end of data to the slave

by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,

the slave must leave the data line high to enable the master to generate the stop condition.

1. The following occurs when data is transferred from a master transmitter to a slave receiver. The first

byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The

slave returns an acknowledge bit after each received byte.

2. The following occurs when data is transferred from a slave transmitter to a master receiver. The

master transmits the first byte (the command/control byte) to the slave. The slave then returns an

acknowledge bit. Next, follows a number of data bytes transmitted by the slave to the master. The

master returns an acknowledge bit after all received bytes other than the last byte. At the end of the

last received byte, a “not acknowledge” can be returned.

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