DS1865 데이터 시트보기 (PDF) - Maxim Integrated
부품명
상세내역
제조사
DS1865 Datasheet PDF : 67 Pages
| |||
PON Triplexer Control and
Monitoring Circuit
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 9.)
PARAMETER
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP and
START Condition
Start Hold Time
Start Setup Time
Data in Hold Time
SYMBOL
fSCL
tLOW
tHIGH
(Note 11)
tBUF
tHD:STA
tSU:STA
tHD:DAT
CONDITIONS
MIN TYP
0
1.3
0.6
1.3
0.6
0.6
0
Data in Setup Time
tSU:DAT
100
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
STOP Setup Time
Capacitive Load for Each Bus Line
EEPROM Write Time
tR
(Note 12)
tF
(Note 12)
tSU:STO
CB
tW
(Note 12)
(Note 13)
20 +
0.1CB
20 +
0.1CB
0.6
MAX
400
UNITS
kHz
µs
µs
µs
µs
µs
0.9
µs
ns
300
ns
300
ns
µs
400
pF
20
ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V)
PARAMETER
SYMBOL
CONDITIONS
EEPROM Write Cycles
At +70°C
MIN TYP
50,000
MAX UNITS
Note 1: All voltages are referenced to ground. Current into IC is positive, out of the IC is negative.
Note 2: Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. DAC1 and M4DAC are not loaded.
Note 3: See the Safety Shutdown (FETG) Output section for details.
Note 4: Eight ranges allow the full-scale range to change from 625mV to 2.5V.
Note 5: This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Note 6: Eight ranges allow the BMD full-scale range to change from 312.5mV to 1.25V.
Note 7: The output impedance of the DS1865 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56kΩ.
Note 8: This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
Note 9: See the APC and Quick-Trip Shared Comparator Timing section for details.
Note 10: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be 1% within the time specified by the binary search time. See the Bias and MOD Output During
Power-Up section.
Note 11: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with the I2C stan-
dard mode.
Note 12: CB⎯total capacitance of one bus line in picofarads.
Note 13: EEPROM write begins after a STOP condition occurs.
Note 14: Guaranteed by design.
_____________________________________________________________________ 5
Share Link: 