LDMOS RF Power-Amplifier Bias
Controller
Pin Description
PIN
NAME
FUNCTION
1
L1
Potentiometer 1 Low Terminal
2
W1
Potentiometer 1 Wiper Terminal
3
W2
Potentiometer 2 Wiper Terminal
4
L2
Potentiometer 2 Low Terminal
5
ID1
Drain Current 1 Monitor Input
6
ID2
Drain Current 2 Monitor Input
7
VD
Drain Voltage Monitor Input
8
GND
Ground
9
FAULT
Fault Output. This open-collector output is active high when one of the enabled alarms is outside its
programmable limit value.
10
A0
11
A1
I2C Address Inputs. These inputs determine the slave address of the device. The slave address in
binary is 1010A2A1A0.
12
A2
13
SCL
Serial Clock Input. I2C clock input.
14
SDA
Serial Data Input/Output. Bidirectional I2C data pin.
15
HCOM Potentiometer High Terminal. Common to potentiometers 1 and 2.
16
VCC
Power Input
8 _____________________________________________________________________