DS2167Q 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2167Q

T1/CEPT Elastic Store

Dallas Semiconductor -> Maxim Integrated 

DS2167/DS2168

both X and Y interfaces, the device enters a low-power

standby mode. The DS2167 will power-up within

200 ms after the X or Y side is reactivated (IPD=0) from

standby. The DS2168 requires an external hardware re-

set after IPD is cleared to “wake-up” from standby. The

DS2168 will power-up immediately after the low-high

transition on RST.

ALRST resets the algorithm coefficients for the selected

channel to their initial values. ALRST will be cleared by

the device when the algorithm reset is complete.

The bypass feature is enabled when BYP is set and IPD

is clear. During bypass, no expansion or compression of

data occurs. This feature allows the user to interchange

timeslots under control of the timeslot registers. Bypass

operates on byte-wide slots when CP/EX=1, on nibble-

wide slots when CP/EX=0.

A-law (µ/A=0) or µ-law PCM (µ/A=1) coding is indepen-

dently selected for the X and Y side interfaces by bit µ/A.

If BYP and IPD are clear, CP/EX determines if input data

is to be compressed or expanded.

TIMESLOT ASSIGNMENT

On-chip counters establish when PCM data I/O occurs

and are programmed via the timeslot registers. Timeslot

size (4 or 8 bits wide) is determined by the state of

CP/EX. Timeslots are counted from the rising edge of

FSX and FSY.

ADDRESS/COMMAND BYTE Figure 3

(MSB)

–

X/Y

A5

A4

A3

A2

A1

SYMBOL

–

X/Y

POSITION

ACB.7

ACB.6

A5

ACB.5

A4

ACB.4

A3

ACB.3

A2

ACB.2

A1

ACB.1

A0

ACB.0

NAME AND DESCRIPTION

Reserved, must be 0 for proper operation.

X/Y Channel Select.

0 = Update channel Y characteristics.

1 = Update channel X characteristics.

MSB of Device Address.

LSB of Device Address.

(LSB)

a0

022698 6/15

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