DS2196 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2196

T1 Dual Framer LIU

Dallas Semiconductor -> Maxim Integrated 

LIST OF TABLES

DS2196

Table 2-1: Pin Description Sorted by Pin Number ................................................................................12

Table 4-1: Register Map Sorted by Address (preliminary address assignment) ................................23

Table 6-1: Output Pin Test Modes ..........................................................................................................39

Table 6-2: Receive Data Source Mux Modes .........................................................................................40

Table 6-3: TPOSB/TNEGB Data Source Select .....................................................................................41

Table 7-1: Receive T1 Level Indication...................................................................................................60

Table 7-2: Alarm Criteria ........................................................................................................................62

Table 8-1: Line Code Violation Counting Arrangements .....................................................................69

Table 8-2: Path Code Violation Counting Arrangements .....................................................................70

Table 8-3: Multiframes Out Of Sync Counting Arrangements ............................................................71

Table 12-1: Transmit Code Length .........................................................................................................78

Table 12-2: Receive Code Length ...........................................................................................................78

Table 15-1: Bert Pattern Select Options .................................................................................................92

Table 15-2: Repetitive Pattern Length Options .....................................................................................93

Table 15-3: Bert Rate Insertion Select ....................................................................................................94

Table 16-1: Error Rate Options.............................................................................................................101

Table 16-2: Error Insertion examples ...................................................................................................102

Table 17-1: Transmit HDLC Configuration ........................................................................................102

Table 18-1: HDLC/BOC Controller Register List ...............................................................................105

Table 20-4: Boundary Scan Register Description ................................................................................133

Table 19-1: Line Build Out Select In LICR..........................................................................................122

Table 19-2: Transformer Specifications ...............................................................................................123

Table 20-1: Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture ............................131

Table 20-2: ID Code Structure...............................................................................................................131

Table 20-3: Device ID Codes ..................................................................................................................132

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