DS2703 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2703

SHA-1 Battery Pack Authentication IC

Dallas Semiconductor -> Maxim Integrated 

DS2703 SHA-1 Battery Pack Authentication IC

SHA Computation

The variables A, B, C, D, E and constants H0, H1, H2, H3, and H4 are initialized as follows:

A

:=

67452301h

H0 :=

67452301h

B

:=

EFCDAB89h

H1 :=

EFCDAB89h

C

:=

98BADCFEh

H2 :=

98BADCFEh

D

:=

10325476h

H3 :=

10325476h

E

:=

C3D2E1F0h

H4 :=

C3D2E1F0h

The final values of variables A, B, C, D, and E are generated by looping through the following set of computations

for t = 0 to 79 (discarding any carry-out). Finally, the H0-H4 constants are added to the A-E variables respectively,

which are then concatenated to form the 160-bit MAC, ABCDE.

for ( t = 0 to 79 )

{

TMP :=

E

:=

D

:=

C

:=

B

:=

A

:=

}

S5(A) + Ft(B,C,D) + Wt + Kt + E

D

C

S30(B)

A

TMP

160-bit MAC := (A+H0) | (B+H1) | (C+H2) | (D+H3) | (E+H4)

DS2703 AUTHENTICATION COMMANDS

WRITE CHALLENGE [0Ch]. This command writes 64 bits in the message block. The LSB of the 64-bit data can

begin immediately after the MSB of the command has been completed. If more than 8 bytes are written, the final

value in the challenge register will be indeterminate. The Compute MAC and Compute Next Secret (with or without

ROM ID) function commands clear the challenge value. Therefore the Write Challenge command must be issued

prior to every Compute MAC or Compute Next Secret command for reliable results.

COMPUTE MAC WITHOUT ROM ID [36h]. This command initiates a SHA-1 computation on the 512 bit block

comprised of words W0 - W15. The 64-bit secret and the 64-bit challenge are loaded in the message block. The

DS2703 takes up to 100us after receiving this command to begin computing the MAC. This gives the host ample

time to connect the DQ pin to a low impedance node prior to the high current demand computation. The DQ pin

must not fall below VPULLUP_MIN during the computation period, tCOMP. The host must release the DQ pin for 1-Wire

data communications (i.e. terminate the low source impedance mode). After the DQ pin has returned to normal

impedance, the host must write eight write zero time slots and then issue 160 read time slots to get the MAC. The

32-bit registers A, B, C, D, and E are used during every cycle of the hash algorithm and their final values at

calculation cycle t=79 are added to the values H0-H4 and stored in registers A-E. The new word ABCDE is now the

MAC. After issuing the command and waiting a minimum of tCOMP, the host reads the 20-byte MAC. This command

allows the use of a master secret and message digest response independent of the ROM ID.

COMPUTE MAC WITH ROM ID [35h]

This command is structured the same as the Compute MAC without ROM ID, except that the ROM ID is loaded to

the message block. Including the ROM ID unique to each DS2703 in the MAC computation allows the use of a

unique secret in each token and a master secret in the host device. See application note “White Paper 4”, available

at http://www.maxim-ic.com, for more information.

SHA-1 related commands used while authenticating a battery or peripheral device are summarized in Table for

convenience. Four additional commands for clearing, computing and locking of the Secret are described in detail in

the following section.

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