DS80C410-FNY 데이터 시트보기 (PDF) - Maxim Integrated
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DS80C410-FNY Datasheet PDF : 102 Pages
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AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)
(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
75MHz
MIN MAX
External Crystal Frequency
VARIABLE CLOCK
MIN
MAX
4
40
UNITS
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
1 / tCLK
16
37.5
MHz
11
18.75
External Clock Oscillator Frequency
DC
75
Clock Mutliplier 2X Mode
1 / tCLK
16
37.5
MHz
Clock Multiplier 4X Mode
11
18.75
ALE Pulse Width
tLHLL
15.0
tCLCL + tCHCL - 5
ns
Port 0 Instruction Address Valid to ALE Low
tAVLL
1.7
tCHCL - 5
ns
Address Hold After ALE Low
tLLAX
4.7
tCLCH - 2
ns
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
14.3
3.7
21.7
8.7
0
8.3
tCLCH - 3
2tCLCL - 5
0
2tCLCL + tCLCH - 19
ns
ns
ns
2tCLCL -18
ns
ns
tCLCL - 5
ns
Port 0 Address to Valid Instruction In
tAVIV0
21.0
3tCLCL - 19
ns
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
tAVIV2
24.7
3tCLCL + tCLCH - 22
ns
PSEN Low to Address Float
tPLAZ
0
0
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production
tested, but are guaranteed by design.
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external clock (tCLK) as defined in
the External Clock Oscillator (XTAL1) Characteristics table.
The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.
All signals guaranteed with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7 (
PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid
bus contention.
References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not
for determing absolute signal timing with respect to the external clock.
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