DSP56300FM 데이터 시트보기 (PDF) - Freescale Semiconductor

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DSP56300FM

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

Phase Lock Loop (PLL) Characteristics

Table 3-5 Clock Operation

No.

Characteristics

Symbol

1 Frequency of EXTAL (EXTAL Pin Frequency)

Ef

The rise and fall time of this external clock should be 3 ns maximum.

2 EXTAL input high1, 2

• With PLL disabled (46.7%–53.3% duty cycle6)

ETH

• With PLL enabled (42.5%–57.5% duty cycle6)

3 EXTAL input low1, 2

• With PLL disabled (46.7%–53.3% duty cycle6)

ETL

• With PLL enabled (42.5%–57.5% duty cycle6)

4 EXTAL cycle time2

• With PLL disabled

ETC

• With PLL enabled

1 Measured at 50% of the input transition.

2 The maximum value for PLL enabled is given for minimum VCO and maximum MF.

Min

0

4.67 ns

4.25 ns

4.67 ns

4.25 ns

10.00 ns

10.00 ns

Max

100.0

∞

157.0 μs

∞

157.0 μs

∞

273.1 μs

3.8 Phase Lock Loop (PLL) Characteristics

Table 3-6 PLL Characteristics

Characteristics

Min

Max

Unit

VCO frequency when PLL enabled (MF × Ef × 2/PDF)

PLL external capacitor (PCAP pin to VCCP) (CPCAP1)

• @ MF ≤ 4

30

200

(MF × 580) − 100

(MF × 780) − 140

MHz

pF

• @ MF > 4

MF × 830

MF × 1470

1 CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for

CPCAP can be computed from one of the following equations:

(MF x 680)-120, for MF ≤ 4, or

MF x 1100, for MF > 4.

DSP56364 Technical Data, Rev. 4.1

3-6

Freescale Semiconductor

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