DTA114EET1(2004) 데이터 시트보기 (PDF) - ON Semiconductor
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DTA114EET1 Datasheet PDF : 12 Pages
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DTA114EET1 Series
Preferred Devices
Bias Resistor Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space. The device is housed in
the SC−75/SOT−416 package which is designed for low power
surface mount applications.
Features
• Pb−Free Packages are Available*
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• The SC−75/SOT−416 package can be soldered using wave or reflow.
The modified gull−winged leads absorb thermal stress during
soldering eliminating the possibility of damage to the die.
• Available in 8 mm, 7 inch/3000 Unit Tape & Reel
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
Collector Current
IC
100 mAdc
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
THERMAL CHARACTERISTICS
Rating
Symbol Value Unit
Total Device Dissipation, FR−4 Board
(Note 1) @ TA = 25°C
Derate above 25°C
PD
200
mW
1.6 mW/°C
Thermal Resistance, Junction−to−Ambient
(Note 1)
RqJA
600 °C/W
Total Device Dissipation, FR−4 Board
(Note 2) @ TA = 25°C
Derate above 25°C
PD
300
mW
2.4 mW/°C
Thermal Resistance, Junction−to−Ambient
(Note 2)
RqJA
400 °C/W
Junction and Storage Temperature Range TJ, Tstg −55 to
°C
+150
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 × 1.0 Inch Pad.
http://onsemi.com
PNP SILICON BIAS
RESISTOR TRANSISTORS
PIN 1
R1
BASE
(INPUT) R2
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
3
2
1
SC−75/SOT−416
CASE 463
STYLE 1
x
M
MARKING
DIAGRAM
xM
= Specific Device Code
= Date Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2004
1
July, 2004 − Rev. 4
Publication Order Number:
DTA114EET1/D
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