TE28F256J3A-115 데이터 시트보기 (PDF) - Intel

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TE28F256J3A-115

Intel StrataFlash® Memory (J3)

Intel 

1.0

1.1

1.2

256-Mbit J3 (x8/x16)

Introduction

This document describes the Intel StrataFlash® Memory (J3) device. It includes a description of

device features, operations, and specifications.

Nomenclature

AMIN:

AMAX:

Block:

Clear:

CUI:

MLC:

OTP:

PLR:

PR:

PRD

Program:

RFU:

Set:

SR:

SRD:

VPEN:

VPEN:

WSM:

ECR:

XSR:

AMIN = A0 for x8

AMIN = A1 for x16

32 Mbit AMAX = A21

64 Mbit AMAX = A22

128 Mbit AMAX = A23

256 Mbit AMAX = A24

A group of flash cells that share common erase circuitry and erase simultaneously

Indicates a logic zero (0)

Command User Interface

Multi-Level Cell

One Time Programmable

Protection Lock Register

Protection Register

Protection Register Data

To write data to the flash array

Reserved for Future Use

Indicates a logic one (1)

Status Register

Status Register Data

Refers to a signal or package connection name

Refers to timing or voltage levels

Write State Machine

Extended Configuration Register

eXtended Status Register

Conventions

0x:

0b:

k (noun):

M (noun):

Nibble

Byte:

Word:

Kword:

Kb:

KB:

Mb:

MB:

Brackets:

Hexadecimal prefix

Binary prefix

1,000

1,000,000

4 bits

8 bits

16 bits

1,024 words

1,024 bits

1,024 bytes

1,048,576 bits

1,048,576 bytes

Square brackets ([]) will be used to designate group membership or to define a

group of signals with similar function (i.e., A[21:1], SR[4,1] and D[15:0]).

Datasheet

7

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