TQ3631 데이터 시트보기 (PDF) - TriQuint Semiconductor
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TQ3631 Datasheet PDF : 10 Pages
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TQ3631
Data Sheet
TQ3631 Product Description
The TQ3631 LNA uses a cascode low noise amplifier along with
signal path switching. A bias control circuit sets the quiescent
current for each mode and ensures peak performance over
process and temperature, see Figure 1. In the application,
CMOS level signals are applied to pins 1 and 5 and are
decoded by an internal logic circuit, this sets the device to the
desired mode. See Table 1 for truth table.
In the high gain mode, switches S1, S2, and S5 are closed, with
switches S3 and S4 open. In the bypass mode, switches S1,
S2, and S5 are open, with switches S3 and S4 closed. Six
internal switches ensures there are no parasitic feedback paths
for the RF signal. In the AMPS mode, control logic switches the
LNA into a low current bias condition.
Only three external components are. The chip uses an external
cap and inductor for the input match to pin 3. The output is
internally matched to 50 ohms at pin 6. A Vdd bypass cap is
required close to pin 8.
External degeneration of the cascode is required between pin 4
and ground. However, a small amount of PC board trace can
be used as the inductor. Alternatively, if an extra component
can be tolerated, a small value chip inductor could be used.
See Figure 2.
VDD
Control
Logic C2
1
Bias and Switch Control Logic
2
GND
LNA IN
L1
3
RFIN
C8
Lbrd
4
DC
GND
S6
S1
S3
S5
S2
S4
R1
VDD
8
C7
7
GND
LNA OUT
6
RF
OUT
Control
5
Logic C3
Figure 1 TQ3631 Simplified Schematic
Operation
MODE
C2
C3
High Gain
0
0
1
0
High Gain
0
1
Low linearity
Bypass
1
1
Typical Gain
13(dB)
11(dB)
-2(dB)
Table 1 LNA States and Control Bits
LNA Input Network Design
Input network design for most LNA’s is a straightforward
compromise between noise figure and gain. The TQ3631 is no
exception, even though it has 3 different modes. The device
was designed so that one only needs to optimize the input
match in the high gain mode. As long as the proper grounding
and source inductance are used, the other two modes will
perform well with the same match.
It is probably wise to synthesize the matching network
component values for some intermediate range of Gamma
values, and then by experimentation, find the one which
provides the best compromise between noise figure and gain.
The quality of the chip ground will have some effect on the
match, which is why some experimentation will likely be needed.
The input match will affect the output match to some degree, so
S22 should be monitored.
The values used on our evaluation board may be used as a
starting point.
Noise Parameter Analysis
A noise parameter analysis is shown on the next page for the
high gain mode. A “nominal” device was mounted directly on an
evaluation board with semi-rigid probes attached to the device
input and output pins. A value of Lbrd was chosen so that
13.0dB of gain was attained at conjugate match. The tuner was
removed and noise data was taken.
6
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