TQ3631 데이터 시트보기 (PDF) - TriQuint Semiconductor
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TQ3631 Datasheet PDF : 10 Pages
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TQ3631
Data Sheet
Gamma Opt analysis for TQ3631 High Gain Mode
Freq.
(MHz)
1800
1960
2040
Opt
0.453
0.459
0.437
Angle
95.8
109.4
116.4
Fmin
(dB)
1.476
1.178
1.287
R noise
14.2
9.58
8.17
Gain Control via Pin 4 Inductance
The source connection of the LNA cascode is brought out
separately through pin 4. That allows the designer to make
some range of gain adjustment. The total amount of inductance
present at the source of the cascode is equal to the bond wire
plus package plus external inductance. One should generally
use an external inductance such that gain in the high gain
CDMA mode = 13.0dB. Although it is possible to increase the
gain of the TQ3631 by using little or no degeneration, input
intercept will be degraded.
Figure 2 shows how a spiral PC board trace can be used as the
external inductance. It is suggested that such a circuit be used
for the initial design prototype. Then the optimum inductance
can be found by simply solder bridging across the inductor. The
final PC board design can then include the proper shorted
version of the inductor.
Figure 2 Showing Lbrd and Grounding on Evaluation Board
Selection of the Vdd Bypass Cap for Optimum
Performance
The Vdd bypass capacitor has the largest effect on the LNA
output match, and is required for proper operation. Because the
input match affects the output match to some degree as well,
the process of picking the bypass cap value involves some
iteration. First, an input match is selected which gives adequate
gain and noise figure. Then the bypass capacitor is varied to
give the best output match. The demo board achieves 11-12dB
of return loss which is adequate for connection directly to the
input of a SAW filter.
Grounding
An optimal ground for the device is important in order to achieve
datasheet specified performance. Symptoms of a poor ground
include reduced gain and the inability to achieve <2:1 VSWR at
the output when the input is matched. It is recommended to use
multiple vias to a mid ground plane layer. The vias at pins 2 and
7 to this layer should be as close to the lead pads as possible
Additionally, the ground return on the Vdd bypass cap should
provide minimal inductance back to chip pins 2 and 7.
TQ3631 S-Parameters
Following are S-Parameter graphs for the high gain and high
mode. Data was taken on a single “nominal” device at 2.8v
Vdd. The reference planes were set at the end of the package
pins.
For additional information and latest specifications, see our website: www.triquint.com
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