RF2196 데이터 시트보기 (PDF) - RF Micro Devices
부품명
상세내역
제조사
RF2196 Datasheet PDF : 8 Pages
| |||
Preliminary
RF2196
Application Schematic
US - CDMA
RF IN
Matching network for
optimum input return loss
Bypassing for
VREG1 and VREG2
15 pF
3.6 pF
TL4
2
Interstage tuning for centering
frequency response
RF Choke - Bias inductor
for the amplifier interstage
VREG
VMODE
+ 1 µF
Jumper
Jumper
1 kΩ
15 pF
15 pF
1 16 15 14 13
2
12
3
11
4
10
56789
11 pF
TL3
10 nF
Ferrite
10 Ω
15 pF
1 µF +
VCC
Bypassing for VCC
Bias return
12 nH
Matching network for
optimum load impedance
Pins 1 and 9 are internally grounded to the die flag.
TL1
4.7 pF
2.5 nH
TL2
2.2 pF
15 pF
10 nF 4.7 µF
2.2 pF
15 pF
RF OUT
Transmission
Line Length
CDMA (US)
TL1
30 mils
TL2
140 mils
TL3
15 mils
TL4
200 mils
Rev A0 010518
2-207
Share Link: 