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EL5130IS-T7(2004) 데이터 시트보기 (PDF) - Intersil

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EL5130IS-T7
(Rev.:2004)
Intersil
Intersil Intersil
EL5130IS-T7 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
EL5130, EL5131
Typical Performance Curves (Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1
0.8 781mW
0.6
SO8
θJA=160°C/W
0.4 488mW
0.2
0
0
SOT23-5
θJA=256°C/W
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
0.03
0.02
0.01
0.00
-0.01
-0.02
-0.03
0
10 20 30 40 50 60 70 80 90 100
FIGURE 26. DIFFERENTIAL GAIN (%)
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
0
10 20 30 40 50 60 70 80 90 100
FIGURE 27. DIFFERENTIAL PHASE (°)
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
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