EL5177(2005) 데이터 시트보기 (PDF) - Intersil
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EL5177 Datasheet PDF : 11 Pages
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EL5177
must be used, a small capacitor in the few Pico farad range
in parallel with RF can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
The bandwidth of the EL5177 depends on the load and the
feedback network. RF and RG appear in parallel with the
load for gains other than +1. As this combination gets
smaller, the bandwidth falls off. Consequently, RF also has a
minimum value that should not be exceeded for optimum
bandwidth performance. For gain of +1, RF = 0 is optimum.
For the gains other than +1, optimum response is obtained
with RF between 500Ω to 1kΩ.
The EL5177 has a gain bandwidth product of 200MHz for
RLD = 1kΩ. For gains ≥5, its bandwidth can be predicted by
the following equation:
Gain × BW = 200MHz
Driving Capacitive Loads and Cables
The EL5177 can drive 23pF differential capacitor in parallel
with 1kΩ differential load with less than 5dB of peaking at
gain of +1. If less peaking is desired in applications, a small
series resistor (usually between 5Ω to 50Ω) can be placed in
series with each output to eliminate most peaking. However,
this will reduce the gain slightly. If the gain setting is greater
than 1, the gain resistor RG can then be chosen to make up
for any gain loss which may be created by the additional
series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5177 can be disabled and placed its outputs in a high
impedance state. The turn off time is about 1.2µs and the
turn on time is about 130ns. When disabled, the amplifier's
supply current is reduced to 1.7µA for IS+ and 120µA for IS-
typically, thereby effectively eliminating the power
consumption. The amplifier's power down can be controlled
by standard CMOS signal levels at the EN pin. The applied
logic signal is relative to VS+ pin. Letting the EN pin float or
applying a signal that is less than 1.5V below VS+ will enable
the amplifier. The amplifier will be disabled when the signal
at EN pin is above VS+ - 0.5V.
Output Drive Capability
The EL5177 has internal short circuit protection. Its typical
short circuit current is ±40mA. If the output is shorted
indefinitely, the power dissipation could easily increase such
that the part will be destroyed. Maximum reliability is
maintained if the output current never exceeds ±40mA. This
limit is set by the design of the internal metal interconnect.
Power Dissipation
With the high output drive capability of the EL5177. It is
possible to exceed the 135°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
PDMAX
=
T----J---M-----A----X-----–-----T----A---M-----A----X--
ΘJA
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
PD
=
VS
×
ISM
A
X
+
VS
×
∆-----V----O--
RLD
Where:
VS = Total supply voltage
ISMAX = Maximum quiescent supply current per channel
∆VO = Maximum differential output voltage of the
application
RLD = Differential load resistance
ILOAD = Load current
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
9
FN7344.3
August 8, 2005
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