EL5224IRE 데이터 시트보기 (PDF) - Intersil
부품명
상세내역
제조사
EL5224IRE Datasheet PDF : 12 Pages
| |||
EL5224, EL5324, EL5424
If the capacitor is increased above 1µF, stability is generally
improved and short pulses of current will cause a smaller
“perturbation” on the VCOM voltage. The speed of response
of the amplifier is however degraded as its bandwidth is
decreased. At capacitor values around 10µF, a subtle
interaction with internal DC gain boost circuitry will decrease
the phase margin and may give rise to some overshoot in
the response. The amplifier will remain stable though.
RESPONSE TO HIGH CURRENT SPIKES
The VCOM amplifier's output current is limited to 150mA.
This limit level, which is roughly the same for sourcing and
sinking, is included to maintain reliable operation of the part.
It does not necessarily prevent a large temperature rise if the
current is maintained. (In this case the whole chip may be
shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than
this limit, the reservoir capacitor will provide the excess and
the amplifier will top the reservoir capacitor back up once the
pulse has stopped. This will happen on the µs time scale in
practical systems and for pulses 2 or 3 times the current
limit, the VCOM voltage will have settled again before the
next line is processed.
Power Dissipation
With the high-output drive capability of the EL5224, EL5324,
and EL5424 buffer, it is possible to exceed the 125°C
“absolute-maximum junction temperature” under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
buffer to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
PDMAX
=
T----J---M-----A----X-----------T----A----M----A----X--
ΘJA
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
PDMAX = Σi × [VS × ISMAX + (VS+ - VOUTi ) × ILOADi ] +
[VSA × ISAA + (VSA + - VOUTA ) × ILA ]
when sourcing, and:
PDMAX = Σi × [VS × ISMAX + (VOUTi - VS- ) × ILOADi ] +
[VSA × ISAA + (VSA + - VOUTA ) × ILA ]
when sinking.
where:
• i = 1 to total number of buffers
• VS = Total supply voltage of buffer
• VSA = Total supply voltage of VCOM
• ISMAX = Maximum quiescent current per channel
• ISA = Maximum quiescent current of VCOM
• VOUTi = Maximum output voltage of the application
• VOUTA = Maximum output voltage of VCOM
• ILOADi = Load current of buffer
• ILA = Load current of VCOM
If we set the two PDMAX equations equal to each other, we
can solve for the RLOAD's to avoid device overheat. The
package power dissipation curves provide a convenient way
to see if the device will overheat. The maximum safe power
dissipation can be found graphically, based on the package
type and the ambient temperature. By using the previous
equation, it is a simple matter to see if PDMAX exceeds the
device's power derating curves.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- and VSA- pins
are connected to ground, two 0.1µF ceramic capacitors
should be placed from VS+ and VSA+ pins to ground. A
4.7µF tantalum capacitor should then be connected from
VS+ and VSA+ pins to ground. One 4.7µF capacitor may be
used for multiple devices. This same capacitor combination
should be placed at each supply pin to ground if split
supplies are to be used. Internally, VS+ and VSA+ are
shorted together and VS- and VSA- are shorted together. To
avoid high current density, the VS+ pin and VSA+ pin must
be shorted in the PCB layout. Also, the VS- pin and VSA- pin
must be shorted in the PCB layout.
Important Note: The metal plane used for heat sinking of
the device is electrically connected to the negative
supply potential (VS- and VSA-). If VS- and VSA- are tied
to ground, the thermal pad can be connected to ground.
Otherwise, the thermal pad must be isolated from any
other power planes.
10
Share Link: 