EL5224IREZ-T13 데이터 시트보기 (PDF) - Intersil
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EL5224IREZ-T13 Datasheet PDF : 12 Pages
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EL5224, EL5324, EL5424
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD. HTSSOP EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3.5
3.333W
3
3.030W
2.5
HTSSOP28
2
θJA=30°C/W
1.5
HTSSOP24
θJA=33°C/W
1
0.5
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
909mW
0.8 833mW
0.7
0.6
HTSSOP28
θJA=110°C/W
0.5
0.4
HTSSOP24
0.3
θJA=120°C/W
0.2
0.1
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Applications Information
Product Description
The EL5224, EL5324, and EL5424 unity gain buffers and
100mA VCOM amplifier are fabricated using a high voltage
CMOS process. The buffers exhibit rail-to-rail input and
output capability and has low power consumption (600µA
per buffer). When driving a load of 10kΩ and 12pF, the
buffers have a -3dB bandwidth of 12MHz and exhibits
18V/µs slew rate. The VCOM amplifier exhibits rail-to-rail
input. The output can be driving to within 2V of each supply
rail. With a 1µF capacitance load, the GBWP is about 1MHz.
Correct operation is guaranteed for a supply range of 4.5V to
16.5V.
The Use of the Buffers
The output swings of the buffers typically extend to within
100mV of positive and negative supply rails with load
currents of 5mA. Decreasing load currents will extend the
output voltage range even closer to the supply rails.
Figure 21 shows the input and output waveforms for the
device. Operation is from ±5V supply with a 10kΩ load
connected to GND. The input is a 10VP-P sinusoid. The
output voltage is approximately 9.985VP-P.
5V
10µs VS=±5V
TA=25°C
VIN=10VP-P
5V
FIGURE 21. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
SHORT-CIRCUIT CURRENT LIMIT
The buffers will limit the short circuit current to ±120mA if the
output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
dissipation could easily increase such that the device may
be damaged. Maximum reliability is maintained if the output
continuous current never exceeds ±30mA. This limit is set by
the design of the internal metal interconnects.
OUTPUT PHASE REVERSAL
The buffers are immune to phase reversal as long as the
input voltage is limited from VS- -0.5V to VS+ +0.5V.
Figure 22 shows a photo of the output of the device with the
input voltage driven beyond the supply rails. Although the
device's output will not change phase, the input's
overvoltage should be avoided. If an input voltage exceeds
supply voltage by more than 0.6V, electrostatic protection
diodes placed in the input stage of the device begin to
conduct and overvoltage damage could occur.
8
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